D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 756
![IC H8S MCU ROMLESS 100-QFP](/photos/28/61/286108/100-tqfp_sml.jpg)
D12312SVTEBL25
Manufacturer Part Number
D12312SVTEBL25
Description
IC H8S MCU ROMLESS 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVTEBL25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412312SVTEBL25
HD6412312SVTEBL25
HD6412312SVTEBL25
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Section 17 ROM
Table 17.53 System Clock Frequency that can Automatically Adjust Bit Rate of This LSI
Bit rate of host
19,200 bps
9,600 bps
State Transition: The overview of the state transition after boot mode is initiated is shown in
figure 17.67. For details on boot mode, refer to section 17.29.1, Serial Communications Interface
Specification for Boot Mode.
[1] Bit rate adjustment
[2] Waiting for inquiry set command
[3] Automatic erasure of all user MAT and user boot MAT
[4] Waiting for programming/erasing command
• When the program preparation notice is received, the state for waiting program data is entered.
• When the erasure preparation notice is received, the state for waiting erase-block data is
• There are many commands other than programming/erasing. Examples are sum check, blank
Rev.7.00 Feb. 14, 2007 page 722 of 1108
REJ09B0089-0700
After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host.
For inquiries about user-MAT size and configuration, MAT start address, and support state, the
required information is transmitted to the host.
After inquiries have finished, all user MAT and user boot MAT are automatically erased.
The programming start address and program data must be transmitted following the
programming command. When programming is finished, the programming start address must
be set to H'FFFFFFFF and transmitted. Then the state for waiting program data is returned to
the state of programming/erasing command wait.
entered. The erase-block number must be transmitted following the erasing command. When
the erasure is finished, the erase-block number must be set to H'FF and transmitted. Then the
state for waiting erase-block data is returned to the state for waiting programming/erasing
command. The erasure must be executed when reset start is not executed and the specified
block is programmed after programming is executed in boot mode. When programming can be
executed by only one operation, all blocks are erased before the state for waiting
programming/erasing/other command is entered. The erasing operation is not required.
check (erasure check), and memory read of the user MAT/user boot MAT and acquisition of
current status information.
System Clock Frequency Which Can Automatically Adjust Bit Rate of
This LSI
16 MHz to 25 MHz
8 MHz to 25 MHz
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