D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 390

• Manufacturer Part Number: D12312SVTEBL25
• Description: IC H8S MCU ROMLESS 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTEBL25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTEBL25; HD6412312SVTEBL25

Section 9 16-Bit Timer Pulse Unit (TPU)
Examples of Cascaded Operation: Figure 9.22 illustrates the operation when counting upon
TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated
as input capture registers, and TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
Figure 9.23 illustrates the operation when counting upon TCNT2 overflow/underflow has been set
for TCNT1, and phase counting mode has been designated for channel 2.
TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow.
Rev.7.00 Feb. 14, 2007 page 356 of 1108
REJ09B0089-0700
TCNT1
clock
TCNT1
TCNT2
clock
TCNT2
TIOCA1,
TIOCA2
TGR1A
TGR2A
H'FFFF
H'03A1
Figure 9.22 Example of Cascaded Operation (1)
H'0000
H'03A2
H'03A2
H'0000
H'0001