D12312SVTEBL25 Renesas Electronics America, D12312SVTEBL25 Datasheet - Page 827

• Manufacturer Part Number: D12312SVTEBL25
• Description: IC H8S MCU ROMLESS 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVTEBL25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412312SVTEBL25; HD6412312SVTEBL25

18.1
The chip has an on-chip clock pulse generator (CPG) that generates the system clock (φ), the bus
master clock, and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-
speed clock divider, and a bus master clock selection circuit.
In the chip, the CPG has a medium-speed mode in which the bus master runs on a medium-speed
clock and the other supporting modules run on the high-speed clock, and a function that allows the
medium-speed mode to be disabled and the clock division ratio to be changed for the entire chip.
A clock from φ/2 to φ/32 can be selected.
18.1.1
Figure 18.1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Overview
Block Diagram
Oscillator
Figure 18.1 Block Diagram of Clock Pulse Generator
Section 18 Clock Pulse Generator
adjustment
circuit
Duty
System clock
to φ pin
speed clock
Medium-
divider
Rev.7.00 Feb. 14, 2007 page 793 of 1108
φ/2 to φ/32
Internal clock
to supporting
modules
Section 18 Clock Pulse Generator
DIV
Bus master
selection
SCKCR
circuit
clock
REJ09B0089-0700
Bus master clock
to CPU and DTC
SCK2 to SCK0