MC9S12C32CFAE16 Freescale Semiconductor, MC9S12C32CFAE16 Datasheet - Page 169

• Manufacturer Part Number: MC9S12C32CFAE16
• Description: IC MCU 32K FLASH 16MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32CFAE16

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 16MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: HCS12
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 2.5|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 31
• Number Of Timers: 8
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

6.3.2
Freescale Semiconductor
BDMCCR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BDMSTS
Register
BDMINR
0xFF0A
0xFF0B
0xFF00
0xFF01
0xFF02
0xFF03
0xFF04
0xFF05
0xFF06
0xFF07
0xFF08
0xFF09
Name
Register Descriptions
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
ENBDM
CCR7
Bit 7
X
X
X
X
X
X
X
X
0
0
0
= Unimplemented, Reserved
= Indeterminate
BDMACT
REG14
CCR6
X
X
X
X
X
X
X
6
0
0
Figure 6-2. BDM Register Summary
MC9S12C-Family / MC9S12GC-Family
ENTAG
REG13
CCR5
X
X
X
X
X
X
X
5
0
0
Rev 01.24
Chapter 6 Background Debug Module (BDMV4) Block Description
REG12
CCR4
SDV
X
X
X
X
X
X
X
4
0
0
TRACE
REG11
CCR3
X
X
X
X
X
X
X
3
0
0
0
= Implemented (do not alter)
= Always read zero
CLKSW
CCR2
2
X
X
X
X
X
0
0
0
X
X
UNSEC
CCR1
1
0
X
X
X
X
0
0
0
X
X
CCR0
Bit 0
X
X
X
X
X
X
0
0
0
0
0
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