MC9S12C32CFAE16 Freescale Semiconductor, MC9S12C32CFAE16 Datasheet - Page 80

• Manufacturer Part Number: MC9S12C32CFAE16
• Description: IC MCU 32K FLASH 16MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32CFAE16

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 16MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: HCS12
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 2.5|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 31
• Number Of Timers: 8
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2
Table 2-2
level (I/O), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports.
The configuration bit PS is used for two purposes:
1. Applicable only on ports P and J.
80
DDR
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
summarizes the effect on the various configuration bits — data direction (DDR), input/output
IO
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
Register Descriptions
All bits of all registers in this module are completely synchronous to internal
clocks during a register read.
RDR
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
PE
X
X
X
X
X
X
X
X
0
1
1
0
0
1
1
PS
X
0
1
0
1
0
1
X
X
X
X
0
1
0
1
Table 2-2. Pin Configuration Summary
MC9S12C-Family / MC9S12GC-Family
IE
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
(1)
Output, reduced drive to 0
Output, reduced drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Rev 01.24
Output, full drive to 0
Output, full drive to 1
Output, full drive to 0
Output, full drive to 1
NOTE
Function
Input
Input
Input
Input
Input
Input
Input
Pull Device
Pull down
Pull down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Pull up
Pull up
Freescale Semiconductor
Falling edge
Rising edge
Falling edge
Falling edge
Rising edge
Falling edge
Rising edge
rising edge
Interrupt
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled