MC9S12C32CFAE16 Freescale Semiconductor, MC9S12C32CFAE16 Datasheet - Page 199

• Manufacturer Part Number: MC9S12C32CFAE16
• Description: IC MCU 32K FLASH 16MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32CFAE16

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 16MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: HCS12
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 2.5|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 31
• Number Of Timers: 8
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
CAPMOD
DBGBRK
Field
1:0
3
DBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint based
on comparator A and B to the CPU upon completion of a tracing session. Please refer to
“Breakpoints,” for further details.
0 CPU break request not enabled
1 CPU break request enabled
Capture Mode Field — See
automatically inhibit redundant entries into capture memory. In detail mode, the debugger is storing address and
data for all cycles except program fetch (P) and free (f) cycles. In profile mode, the debugger is returning the
address of the last instruction executed by the CPU on each access of trace buffer address. Refer to
Section 7.4.2.6, “Capture
Table 7-3. DBGC1 Field Descriptions (continued)
Modes,” for more information.
MC9S12C-Family / MC9S12GC-Family
Table 7-4
CAPMOD
Table 7-4. CAPMOD Encoding
00
01
10
11
for capture mode field definitions. In LOOP1 mode, the debugger will
Rev 01.24
Description
Description
PROFILE
LOOP1
DETAIL
Normal
Chapter 7 Debug Module (DBGV1) Block Description
Section 7.4.3,
199