DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 218

• Manufacturer Part Number: DF36054GFPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054GFPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Timer Z
Note: Bit 5 is not the UDF flag in TSR_0. It is a reserved bit. It is always read as 1.
12.3.12 Timer Interrupt Enable Register (TIER)
TIER enables or disables interrupt requests for overflow or GR compare match/input capture.
Timer Z has two TIER registers, one for each channel.
Rev. 4.00 Mar. 15, 2006 Page 184 of 556
REJ09B0026-0400
Bit
0
Bit
7 to 5
4
3
2
1
Bit Name
IMFA
Bit Name
OVIE
IMIED
IMIEC
IMIEB
Initial
Value
0
Initial
Value
All 1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Input Capture/Compare Match Flag A
[Setting conditions]
[Clearing condition]
Description
Reserved
These bits are always read as 1.
Overflow Interrupt Enable
0: Interrupt requests (OVI) by OVF or UDF flag are
1: Interrupt requests (OVI) by OVF or UDF flag are
Input Capture/Compare Match Interrupt Enable D
0: Interrupt requests (IMID) by IMFD flag are disabled
1: Interrupt requests (IMID) by IMFD flag are enabled
Input Capture/Compare Match Interrupt Enable C
0: Interrupt requests (IMIC) by IMFC flag are disabled
1: Interrupt requests (IMIC) by IMFC flag are enabled
Input Capture/Compare Match Interrupt Enable B
0: Interrupt requests (IMIB) by IMFB flag are disabled
1: Interrupt requests (IMIB) by IMFB flag are enabled
disabled
enabled
When TCNT = GRA and GRA is functioning as output
compare register
When TCNT value is transferred to GRA by input
capture signal and GRA is functioning as input
capture register
When 0 is written to IMFA after reading IMFA = 1