DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 454

• Manufacturer Part Number: DF36054GFPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054GFPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 21 List of Registers
Rev. 4.00 Mar. 15, 2006 Page 420 of 556
REJ09B0026-0400
Register Name
General register C_0
General register D_0
Timer control register_1
Timer I/O control register A_1
Timer I/O control register C_1
Timer status register_1
Timer interrupt enable register_1
PWM mode output level control
register_1
Timer counter_1
General register A_1
General register B_1
General register C_1
General register D_1
Timer start register
Timer mode register
Timer PWM mode register
Timer function control register
Timer output master enable register TOER
Timer output control register
—
Low-voltage-detection control
register
Low-voltage-detection status
register
—
Serial mode register_2
Bit rate register_2
Serial control register 3_2
Transmit data register_2
Abbre-
viation
GRC_0
GRD_0
TCR_1
TIORA_1 8
TIORC_1 8
TSR_1
TIER_1
POCR_1 8
TCNT_1 16
GRA_1
GRB_1
GRC_1
GRD_1
TSTR
TMDR
TPMR
TFCR
TOCR
—
LVDCR
LVDSR
—
SMR_2
BRR_2
SCR3_2 8
TDR_2
Bit No Address
16
16
8
8
8
16
16
16
16
8
8
8
8
8
8
—
8
8
—
8
8
8
H'F710
H'F711
H'F712
H'F713
H'F714
H'F715
H'F716
H'F720
H'F721
H'F722
H'F723
H'F724
H'F725
H'F726 to
H'F72F
H'F730
H'F731
H'F732 to
H'F73F
H'F740
H'F741
H'F742
H'F743
H'F70C
H'F70E
H'F718
H'F71A
H'F71C
H'F71E
Module
Name
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
—
LVDC*
LVDC*
—
SCI3_2*
SCI3_2*
SCI3_2*
SCI3_2*
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
Timer Z
1
1
3
3
3
3
Data
Bus
Width
16
16
8
8
8
8
8
8
16
16
16
16
16
8
8
8
8
8
8
—
8
8
—
8
8
8
8
Access
State
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
2
2
—
3
3
3
3