DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 316

MCU 3/5V 32K J-TEMP PB-FREE 64-L

DF36054GFPJV

Manufacturer Part Number
DF36054GFPJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of DF36054GFPJV

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 4.00 Mar. 15, 2006 Page 282 of 556
REJ09B0026-0400
[4]
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
Yes
No
Read receive data in RDR
Clear OER flag in SSR to 0
Clear RE bit in SCR3 to 0
Read RDRF flag in SSR
Overrun error processing
Read OER flag in SSR
All data received?
Error processing
Start reception
RDRF = 1
OER = 1
<End>
<End>
Yes
No
No
(Continued below)
Error processing
Yes
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[4]
Read the OER flag in SSR to determine if
there is an error. If an overrun error has
occurred, execute overrun error processing.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR.
When data is read from RDR, the RDRF
flag is automatically cleared to 0.
To continue serial reception, before the
MSB (bit 7) of the current frame is received,
reading the RDRF flag and reading RDR
should be finished. When data is read from
RDR, the RDRF flag is automatically
cleared to 0.
If an overrun error occurs, read the OER
flag in SSR, and after performing the
appropriate error processing, clear the OER
flag to 0. Reception cannot be resumed if
the OER flag is set to 1.

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