DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 58

MCU 3/5V 32K J-TEMP PB-FREE 64-L

DF36054GFPJV

Manufacturer Part Number
DF36054GFPJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of DF36054GFPJV

Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 2 CPU
Table 2.3
[Legend]
B: Byte
W: Word
L: Longword
Note:
Rev. 4.00 Mar. 15, 2006 Page 24 of 556
REJ09B0026-0400
Instruction
DIVXS
CMP
NEG
EXTU
EXTS
*
Refers to the operand size.
Arithmetic Operations Instructions (2)
W/L
W/L
Size*
B/W
B/W/L
B/W/L
Function
Rd ÷ Rs
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits
quotient and 16-bit remainder.
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to the
result.
0 – Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
Rd (zero extension)
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
Rd (sign extension)
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
Rd
8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits
Rd
Rd
Rd
16-bit

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