DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 291

• Manufacturer Part Number: DF36054GFPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054GFPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.3.6
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. For details on interrupt requests, refer to section 14.7,
Interrupts.
Bit
1
0
Bit
7
6
5
4
Bit Name
CKS1
CKS0
Bit Name
TIE
RIE
TE
RE
Serial Control Register 3 (SCR3)
Initial
Value
0
0
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Clock Select 0 and 1
These bits select the clock source for the baud rate
generator.
00:
01: /4 clock (n = 1)
10: /14 clock (n = 2)
11: /64 clock (n = 3)
For the relationship between the bit rate register setting
and the baud rate, see section 14.3.8, Bit Rate Register
(BRR). n is the decimal representation of the value of n in
BRR (see section 14.3.8, Bit Rate Register (BRR)).
Description
Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
Transmit Enable
When this bit s set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
clock (n = 0)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 4.00 Mar. 15, 2006 Page 257 of 556
REJ09B0026-0400