DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 73

• Manufacturer Part Number: DF36054GFPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054GFPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.6.2
On-chip peripheral modules are accessed in two states, three states, or four states. The data bus
width is 8 bits or 16 bits depending on the register. For description on the data bus width and
number of accessing states of each register, refer to section 21.1, Register Addresses (Address
Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-
bit data bus width can be accessed by byte or word size. When a register with 8-bit data bus width
is accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the
same as that for on-chip memory. Figure 2.10 shows the operation timing in the case of three-state
access to an on-chip peripheral module. In four-state access, the operation timing is such that a
wait cycle is inserted between the T
On-Chip Peripheral Modules
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Internal
data bus
(write access)
or
SUB
T
1
state
2
and T
3
states.
Address
Bus cycle
T
2
state
Read data
Write data
Rev. 4.00 Mar. 15, 2006 Page 39 of 556
T
3
state
REJ09B0026-0400
Section 2 CPU