DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 253
![MCU 3/5V 32K J-TEMP PB-FREE 64-L](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36054GFPJV
Manufacturer Part Number
DF36054GFPJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36054GFPJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when
the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been
designated for BR, BR is transferred to GR when the counter is incremented by compare match
A0 or when TCNT_1 is underflowed.
If the or /2 clock is selected by TPSC2 to TPSC0 bits, the OVF flag is not set to 1 at the timing
that the counter value changes from H'FFFF to H'0000. If the /4 or /8 clock is selected by
TPSC2 to TPSC0 bits, the OVF flag is set to 1.
Setting GR Value in Complementary PWM Mode: To set GR or modify GR during operation
in complementary PWM mode, refer to the following notes.
1. Initial value
2. Modifying the setting value
3. Outputting a waveform with a duty cycle of 0% and 100%
A. When buffer operation is not used and TPSC2 = TPSC1 = TPSC0 = 0.
When other than TPSC2 = TPSC1 = TPSC0 = 0, the GRA_0 value must be equal to
H'FFFC or less. When TPSC2 = TPSC1 = TPSC0 = 0, the GRA_0 value can be set to
H'FFFF or less.
H'0000 to T – 1 (T: Initial value of TCNT0) must not be set for the initial value.
GRA_0 – (T – 1) or more must not be set for the initial value.
When using buffer operation, the same values must be set in the buffer registers and
corresponding general registers.
Writing to GR directly must be performed while the TCNT_1 and TCNT_0 values should
satisfy the following expression: H'0000 TCNT_1 < previous GR value, and previous GR
value < TCNT_0 GRA_0. Otherwise, a waveform is not output correctly. For details on
outputting a waveform with a duty cycle of 0% and 100%, see 3., Outputting a waveform
with a duty cycle of 0% and 100%.
Do not write the following values to GR directly. When writing the values, a waveform is
not output correctly.
H'0000 GR T – 1 and GRA_0 – (T – 1) GR < GRA_0 when TPSC2 = TPSC1 =
TPSC0 = 0
H'0000 < GR T – 1 and GRA_0 – ( T – 1)
TPSC0 = 0
Do not change settings of GRA_0 during operation.
Write H'0000 or a value equal to or more than the GRA_0 value to GR directly at the
timing shown below.
To output a 0%-duty cycle waveform, write a value equal to or more than the GRA_0
value while H'0000 TCNT_1 < previous GR value.
GR < GRA_0 + 1 when TPSC2 = TPSC1 =
Rev. 4.00 Mar. 15, 2006 Page 219 of 556
Section 12 Timer Z
REJ09B0026-0400
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