DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 366

• Manufacturer Part Number: DF36054GFPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054GFPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Controller Area Network for Tiny (TinyCAN)
HRXD
HTXD
TXPR.MBn
TXCR.MBn
DART
ABACK.MBn
TCIRR.EMPI
TXACK.MBn
CAN Bus Error: Figures 15.11 to 15.13 show timings for internal arbitration caused by an error
on the CAN bus. Procedure and operation are as follows.
1. Write data of a transmit message to MCn0, MCn4 to MCn7, and MDn0 to MDn7 [n = 1 to 3]
2. Set the MBn bit in TXPR to 1 (start condition issuance). Then, the start condition is generated.
3. The internal arbitration for message 1 is determined and the transmit message is transferred to
Rev. 4.00 Mar. 15, 2006 Page 332 of 556
REJ09B0026-0400
[2] Set TXPR
Figure 15.10 Internal Arbitration at Reception Caused by CAN Bus Arbitration Loss
before clearing the MBn bit in MBCR corresponding to the Mailbox of the transmit message to
0 (initial setting).
the temporary buffer. After that, even if a transmit request cancellation is issued to the message
being transmitted by the DART or MBn bit in TXCR, message 1 is transmitted continuously
unless the TinyCAN detects an arbitration loss or error on the CAN bus.
Bus idle
Bus idle
[3] Load DART bit when message 1
is transferred to temporary buffer
Transmission for message 1
cannot be cancelled by TXCR
(Transmission settings can be changed by TXPR/TXCR)
SOF
SOF
Internal arbitration for message 2 can be configurable
Arbitration
Arbitration
Control
[4] Arbitration loss
[4] Clear MBn bit in TXPR for message 1
[4] Set MBn in ABACK and EMPI in TCIRR1 for message 1
(DART = 1)
Message 1
ACK Bit
Message 1 reception
Data
CRC
ACK
EOF
[5] Internal arbitration for message 2
[5] Overwrite DART bit for message 2
Intermission
is determined after normal reception
has completed
If other Mailbox has a transmit
request, transmission is started at this
timing
Transmission for message 2
cannot be cancelled by TXCR
Internal arbitration for message 3
can be configurable
SOF
Message 2