DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 23

• Manufacturer Part Number: DF36054GFPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054GFPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figures
Section 1 Overview
TM
Figure 1.1 Internal Block Diagram of F-ZTAT
and Masked ROM Versions ............................ 3
TM
Figure 1.2 Pin Arrangement of F-ZTAT
and Masked ROM Versions (FP-64K, FP-64A)......... 4
Section 2 CPU
Figure 2.1 Memory Map (1) ......................................................................................................... 11
Figure 2.1 Memory Map (2) ......................................................................................................... 12
Figure 2.1 Memory Map (3) ......................................................................................................... 13
Figure 2.2 CPU Registers ............................................................................................................. 14
Figure 2.3 Usage of General Registers ......................................................................................... 15
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 16
Figure 2.5 General Register Data Formats (1).............................................................................. 18
Figure 2.5 General Register Data Formats (2).............................................................................. 19
Figure 2.6 Memory Data Formats................................................................................................. 20
Figure 2.7 Instruction Formats...................................................................................................... 31
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 35
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 38
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 39
Figure 2.11 CPU Operation States................................................................................................ 40
Figure 2.12 State Transitions ........................................................................................................ 41
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same
Address...................................................................................................................... 43
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 61
Figure 3.2 Stack Status after Exception Handling ........................................................................ 63
Figure 3.3 Interrupt Sequence....................................................................................................... 64
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 65
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 67
Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 71
Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 72
Section 5 Clock Pulse Generators
Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 73
Figure 5.2 Block Diagram of System Clock Generator ................................................................ 74
Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 74
Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 74
Rev. 4.00 Mar. 15, 2006 Page xxi of xxxii