DF36054GFPJV Renesas Electronics America, DF36054GFPJV Datasheet - Page 304
![MCU 3/5V 32K J-TEMP PB-FREE 64-L](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36054GFPJV
Manufacturer Part Number
DF36054GFPJV
Description
MCU 3/5V 32K J-TEMP PB-FREE 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36054GFPJV
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 304 of 594
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Section 14 Serial Communication Interface 3 (SCI3)
14.4
Figure 14.2 shows the general format for asynchronous serial communication. One character (or
frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or
low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are
independent units, enabling full-duplex. Both the transmitter and the receiver also have a double-
buffered structure, so data can be read or written during transmission or reception, enabling
continuous data transfer.
14.4.1
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3’s serial clock, according to the setting of the COM bit in
SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin, the
clock frequency should be 14 times the bit rate used.
When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 14.3.
Rev. 4.00 Mar. 15, 2006 Page 270 of 556
REJ09B0026-0400
Clock
Serial data
Serial
data
Figure 14.3 Relationship between Output Clock and Transfer Data Phase
Operation in Asynchronous Mode
Clock
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
Start
bit
1 bit
Figure 14.2 Data Format in Asynchronous Communication
LSB
0
D0
One unit of transfer data (character or frame)
D1
Transmit/receive data
D2
7 or 8 bits
D3
1 character (frame)
D4
D5
D6
MSB
D7
Parity
bit
1 bit,
or none
0/1
1
Stop bit
1 or
2 bits
1
Mark state
1
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