DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 17

• Manufacturer Part Number: DF2238RTF6
• Description: MCU 2.2/3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2238RTF6

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 6MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2238RTF6; HD64F2238RTF6

Item
16.3.6 I
Register (ICCR)
16.4.6 Slave Transmit
Operation
16.6 Usage Notes
Table 16.7 I
(SCL and SDA Output)
2
C Bus Control
2
C Bus Timing
Page
644
670
671
677
Revision (See Manual for Details)
Table amended
Description added
1. Initialize slave receive mode and wait for slave address
Description amended
4. The master device drives SDA low at the 9th clock pulse,
Description added
10. When the stop condition is detected, that is, when SDA
Table amended
Bit
7
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
and returns an acknowledge signal. When the value of
the ACKE bit in ICSR is 1, the acknowledge signal state
is stored in the ACKB bit, so the ACKB bit can be used to
determine whether the transfer operation was performed
successfully.
reception.
When making initial settings for slave receive mode, set
the ACKE bit in ICCR to 1. This is necessary in order to
enable reception of the acknowledge bit after entering
slave transmit mode.
Bit Name
ICE
is changed from low to high when SCL is high, the
BBSY flag in ICCR is cleared to 0 and the STOP flag in
ICSR is set to 1. At the same time, the IRIC flag is set to
1. If the IRIC flag has been set, it is cleared to 0.
To restart slave transmit mode operation, make the
initial settings once again.
Initial
Value
0
R/W
R/W
Rev. 6.00 Mar. 18, 2010 Page xv of lx
Description
I
When this bit is set to 1, the I
enabled to send/receive data and drive the bus since it is
connected to the SCL and SDA pins. ICMR and ICDR can be
accessed.
SCL and SDA output is disabled (and input to SCL and SDA is
enabled) when this bit is cleared to 0. SAR and SARX can be
accessed.
Symbol
t
t
t
2
SCLO
SCLHO
SCLLO
C Bus Interface Enable
Output Timing
28 t
0.5 t
0.5 t
cyc
SCLO
SCLO
to 256 t
cyc
2
C bus interface module is
REJ09B0054-0600
Unit
ns
ns
ns
Notes
Figure 27.34