DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 591

• Manufacturer Part Number: DF2238RTF6
• Description: MCU 2.2/3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2238RTF6

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 6MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2238RTF6; HD64F2238RTF6

14.4.2
This section describes an example of performing a slave reception using the DTC.
(1) IEB Initialization
(a) Setting the IEBus Control Register (IECTR)
(b) Setting the IEBus Master Unit Address Registers 1 and 2 (IEAR1 and IEAR2)
(c) Setting the IEBus Receive Interrupt Enable Register (IEIER)
Enable the IEBus pins, select the signal polarity, and select a clock supplied to the IEB. Set the
RE bit to 1 to perform reception. The LUEE bit does not need to be specified.
Specify the master unit address and specify the communications mode in IEAR1. Compare
with the slave address in the communications frame and receive the frame if matched.
Enable RxRDY (IERxI), RxS, and RxE (IERSI) interrupts.
Interrupt
IETxI (TxRDY)
(TO DTC)
IETxI (TxRDY)
(TO CPU)
IETSI
(TO CPU)
IECMR
IETSR
IEFLG
TxRDY
Slave Receive Operation
MRQ
CMX
SRQ
SRE
TxS
TxF
LF
Slave reception
Cleared to 0 byt DTC transfer of 1st byte
(1)
H: Header, MA: Master address field, SA: Slave address field,
CF: Control field, LF: Message length field, D1, D2,..., Dn-1, Dn: Data field
Master transmission request
Figure 14.8 Master Transmit Operation Timing
Dn-1
Dn
(2)
(2)
H
MA
(3)
(3)
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
SA
CF
DTC transfer
Master transmission
of 2nd byte
LF
Rev. 6.00 Mar. 18, 2010 Page 529 of 982
(4)
(4)
D1
(5)
(5)
DTC transfer
of 3rd byte
D2
(6)
(6)
(7)
DTC transfer
Dn-1
of nth byte
REJ09B0054-0600
Dn
(8)
(8)