DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 633
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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15.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 15.2 The Relationships between the N Setting in BRR and Bit Rate B
Legend:
B:
N:
φ:
n and S: Determined by the SMR settings shown in the following tables.
Note:
Communication
Mode
Asynchronous
Mode
Clocked
Synchronous
Mode
Smart Card
Interface Mode
CKS1
0
0
1
1
SMR Setting
* If the ABCS bit is set to 1, SCI_0 on the H8S/2239 Group only valid bit rate.
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Bit Rate Register (BRR)
CKS0
0
1
0
1
ABCS bit *
0
1
⎯
⎯
Clock
Source
φ
φ/4
φ/16
φ/64
Bit Rate
n
0
1
2
3
B =
B =
B =
B =
64 × 2
32 × 2
S × 2
8 × 2
2n−1
φ × 10
φ × 10
φ × 10
φ × 10
2n+1
2n−1
2n−1
× (N + 1)
× (N + 1)
× (N + 1)
× (N + 1)
Section 15 Serial Communication Interface (SCI)
6
6
6
6
Rev. 6.00 Mar. 18, 2010 Page 571 of 982
BCP1
0
0
1
1
Error
⎯
Error (%) = {
Error (%) = {
Error (%) = {
SMR Setting
BCP0
0
1
0
1
B × 64 × 2
B × 32 × 2
B × S × 2
φ × 10
φ × 10
φ × 10
2n+1
2n−1
2n−1
REJ09B0054-0600
S
32
64
372
256
6
6
6
× (N + 1)
× (N + 1)
× (N + 1)
−1 } × 100
−1 } × 100
−1 } × 100
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