DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 260

MCU 2.2/3V 256K 100-TQFP

DF2238RTF6

Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of DF2238RTF6

Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 Bus Controller
Figure 7.24 shows the timing for transition to the bus-released state.
7.9.1
When MSTPCR is set to H'FFFFFF and transmitted to sleep mode, the external bus release does
not function. To activate the external bus release in sleep mode, do not set MSTPCR to H'FFFFFF.
Rev. 6.00 Mar. 18, 2010 Page 198 of 982
REJ09B0054-0600
Address bus
HWR, LWR
Data bus
Bus Release Usage Note
Note : n = 7 to 0
[1]
[2]
[3]
[4]
[5]
BREQ
BACK
CSn
RD
AS
φ
Low level of BREQ pin is sampled at rise of T
BACK pin is driven low at end of CPU read cycle, releasing bus to external bus
master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
Figure 7.24 Bus-Released State Transition Timing
T
0
CPU cycle
T
Address
1
[1]
Minimum
1 state
T
2
2
[2]
state.
External bus released state
[3]
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
[4]
CPU
cycle
[5]

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