DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 227

• Manufacturer Part Number: DF2238RTF6
• Description: MCU 2.2/3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2238RTF6

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 6MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2238RTF6; HD64F2238RTF6

This LSI has a built-in bus controller (BSC) that manages the external address space divided into
eight areas. The bus controller also has a bus arbitration function, and controls the operation of the
internal bus masters: the CPU, DMA controller (DMAC)*, and data transfer controller (DTC).
Note: * Supported only by the H8S/2239 Group.
7.1
• Manages external address space in area units
• Basic bus interface
• Burst ROM interface
• Idle cycle insertion
• Bus arbitration
• Other features
Note: * Supported only by the H8S/2239 Group.
⎯ Manages the external space as 8 areas of 2-Mbytes
⎯ Bus specifications can be set independently for each area
⎯ Burst ROM interface can be set
⎯ Chip select (CS7 to CS0) can be output for areas 7 to 0
⎯ 8-bit access or 16-bit access can be selected for each area
⎯ 2-state access or 3-state access can be selected for each area
⎯ Program wait states can be inserted for each area
⎯ Burst ROM interface can be selected for area 0
⎯ One or two states can be selected for the burst cycle
⎯ Idle cycle can be inserted between consecutive read accesses to different areas
⎯ Idle cycle can be inserted before a write access to an external area immediately after a read
⎯ The on-chip bus arbiter arbitrates bus mastership among CPU, DMAC*, and DTC.
⎯ External bus release function
access to an external area
Features
Section 7 Bus Controller
Rev. 6.00 Mar. 18, 2010 Page 165 of 982
Section 7 Bus Controller
REJ09B0054-0600