DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 598

MCU 2.2/3V 256K 100-TQFP

DF2238RTF6

Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of DF2238RTF6

Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
14.4.4
This section shows an example of performing a slave transmission using the DTC after slave
reception.
(1) IEB Initialization
(a) Setting the IEBus Control Register (IECTR)
(b) Setting the IEBus Master Unit Address Registers 1 and 2 (IEAR1 and IEAR2)
Rev. 6.00 Mar. 18, 2010 Page 536 of 982
REJ09B0054-0600
Enable the IEBus pins, select the signal polarity, and select a clock supplied to the IEB. Clear
the LUEE bit to 0 because transfer by the DTC is performed.
Specify the master unit address and specify the communications mode in IEAR1. Compare
with the slave address in the communications frame and receive the frame if matched.
Interrupt
IERxI (RxRDY)
(TO DTC)
IERxI (RxRDY)
(TO CPU)
IERSI
(TO CPU)
IECMR
IERSR
IECTR
IEFLG
RxRDY
Slave Transmission
MRQ
CMX
SRQ
SRE
RxS
RxF
RE
Slave reception
H: Header, MA: Master address field, SA: Slave address field,
CF: Control field, LF: Message length field, D1, D2,..., Dn-1, Dn: Data field
(1)
Master reception request
Figure 14.11 Master Receive Operation Timing
Dn
(2)
(2)
H
MA
SA
CF
(3)
Master reception
LF
(4)
(4)
DTC transfer
of 1st byte
D1
(5)
(5)
D2
of (n-2)th byte
DTC transfer
(6)
(6)
Dn-1
of (n-1)th byte
DTC transfer
Dn
(9)
(7)
(7)
(9)
(8)
DTC transfer
(9)
of nth byte

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