DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 740

• Manufacturer Part Number: DF2238RTF6
• Description: MCU 2.2/3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2238RTF6

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 6MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2238RTF6; HD64F2238RTF6

Section 16 I
Table 16.8 Permissible SCL Rise Time (t
IICX
0
1
Notes: 1. Supported only by the H8S/2239 Group.
6. The I
Rev. 6.00 Mar. 18, 2010 Page 678 of 982
REJ09B0054-0600
and 300 ns. The I
table 16.7. However, because of the rise and fall times, the I
not be satisfied at the maximum transfer rate. Table 16.9 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times. The
values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to
CKS2. Depending on the frequency it may not be possible to achieve the maximum transfer
rate; therefore, whether or not the I
in accordance with the actual setting conditions.
t
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t
specifications for worst-case calculations of t
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing permits this output timing for use as slave devices connected to the I
BUFO
SCLLO
t
Indication
7.5 t
17.5 t
cyc
2. The H8S/2258 Group is out of operation.
fails to meet the I
in high-speed mode and t
2
cyc
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
cyc
2
C Bus Interface (IIC) (Option)
Normal mode
High-speed mode300 ns
Normal mode
High-speed mode300 ns
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
I
Specification
(Max)
1000 ns
1000 ns
2
C Bus
STASO
2
in standard mode fail to satisfy the I
C bus interface specifications are met must be determined
sr
) Values
φ =
5 MHz *
1000 ns
300 ns
1000 ns
300 ns
Sr
/t
Sf
. Possible solutions that should be investigated
2
φ =
8 MHz *
937 ns
300 ns
1000 ns
300 ns
Time Indication
2
C bus interface specifications may
2
φ =
10 MHz
750 ns
300 ns
1000 ns
300 ns
2
C bus.
2
C bus interface
φ =
16 MHz *
468 ns
300 ns
1000 ns
300 ns
2
C bus.
cyc
, as shown in
1
φ =
20 MHz *
375 ns
300 ns
875 ns
300 ns
1