DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 649
DF2238RTF6
Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2238RTF6
Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6
HD64F2238RTF6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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15.4.2
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer
rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and
performs internal synchronization. Receive data is latched internally at the rising edge of the 8th
pulse of the base clock as shown in figure 15.6. Thus, the reception margin in asynchronous mode
is given by formula (1) below.
M = (0.5 −
Where M: Reception margin (%)
Assuming values of F (absolute value of clock rate deviation) = 0, D (clock duty) = 0.5, and N
(ratio of bit rate to clock) = 16 in formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
Note: Example for H8S/2239 Group with the ABCS bit in SEMR_0 set to a value other than 1.
When ABCS is set to 1, the clock frequency is 8 times the bit rate and sampling of
received data takes place at the fourth rising edge of the basic clock.
N: Bit rate ratio relative to clock (N = 16, but in the H8S/2239 Group N = 8 if ABCS in
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Clock frequency deviation absolute value
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
SEMR_0 is set to 1.)
2N
1
) − (L − 0.5) F −
D − 0.5
N
(1 + F) × 100 [%]
Section 15 Serial Communication Interface (SCI)
Rev. 6.00 Mar. 18, 2010 Page 587 of 982
... Formula (1)
REJ09B0054-0600
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