DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 743

• Manufacturer Part Number: DF2238RTF6
• Description: MCU 2.2/3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2238RTF6

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 6MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2238RTF6; HD64F2238RTF6

8. Notes on Start Condition Issuance for Retransmission
Depending on the timing combination with the start condition issuance and the subsequently
writing data to ICDR, it may not be possible to issue the retransmission and the data
transmission after retransmission condition issuance.
After start condition issuance is done and determined the start condition, write the transmit
data to ICDR, as shown below. Figure 16.22 shows the timing of start condition issuance for
retransmission, and the timing for subsequently writing data to ICDR, together with the
corresponding flowchart.
Figure 16.22 Flowchart and Timing of Start Condition Instruction Issuance for
IRIC
SDA
SCL
Write transmit data to ICDR
[1] IRIC determination
Yes
Yes
Clear IRIC in ICSR
Write BBSY = 1,
SCP = 0 (ICSR)
ACK
Read SCL pin
Start condition
SCL = Low?
IRIC = 1?
issuance?
IRIC = 1?
9
Yes
Yes
[2] Detemination of SCL = Low
[3] (Restart) Start condition instruction issuance
No
No
No
No
Other processing
[1]
[2]
[3]
[4]
[5]
Retransmission
Start condition
(retransmission)
[4] IRIC determination
[1] Wait for end of 1-byte transfer
[2] Determine whether SCL is low
[3] Issue restart condition instruction for transmission
[4] Determine whether start condition is generated or not
[5] Set transmit data (slave address + R/W)
Note: Program so that processing from [3] to [5]
Section 16 I
Rev. 6.00 Mar. 18, 2010 Page 681 of 982
is executed continuously.
[5] ICDR write (next transmit data)
Data output
2
C Bus Interface (IIC) (Option)
Bit 7
REJ09B0054-0600