DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 466

MCU 2.2/3V 256K 100-TQFP

DF2238RTF6

Manufacturer Part Number
DF2238RTF6
Description
MCU 2.2/3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of DF2238RTF6

Core Processor
H8S/2000
Core Size
16-Bit
Speed
6MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2238RTF6
HD64F2238RTF6

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2238RTF6V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 11 16-Bit Timer Pulse Unit (TPU)
Example of Synchronous Operation: Figure 11.12 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOCA2, TIOCA1, and TIOCA0. At this
time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed
for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle.
Rev. 6.00 Mar. 18, 2010 Page 404 of 982
REJ09B0054-0600
[1]
[2]
[3]
[4]
[5]
Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation.
When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is
simultaneously written to the other TCNT counters.
Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc.
Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
<Synchronous presetting>
Synchronous presetting
Synchronous operation
Set synchronous
Figure 11.11 Example of Synchronous Operation Setting Procedure
Set TCNT
operation
selection
[1]
[2]
Synchronous clearing
<Counter clearing>
source generation
clearing source
Select counter
Start count
channel?
Clearing
Yes
No
[3]
[5]
<Synchronous clearing>
Set synchronous
counter clearing
Start count
[4]
[5]

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