DF2238RTF6 Renesas Electronics America, DF2238RTF6 Datasheet - Page 874

• Manufacturer Part Number: DF2238RTF6
• Description: MCU 2.2/3V 256K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2238RTF6

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 6MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2238RTF6; HD64F2238RTF6

Section 26 List of Registers
Rev. 6.00 Mar. 18, 2010 Page 812 of 982
REJ09B0054-0600
Register Name
Timer control register_5
Timer mode register_5
Timer I/O control register_5
Timer interrupt enable register_5
Timer status register_5
Timer counter_5
Timer general register A_5
Timer general register B_5
Timer start register
Timer synchro register
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
Interrupt priority register I
Interrupt priority register J
Interrupt priority register K
Interrupt priority register L
Interrupt priority register O
Bus width control register
Access state control register
Wait control register H
Wait control register L
Bus control register H
Bus control register L
RAM emulation register
Memory address register_0AH
Memory address register_0AL
Abbrevia-
tion
TCR_5
TMDR_5
TIOR_5
TIER_5
TSR_5
TCNT_5
TGRA_5
TGRB_5
TSTR
TSYR
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRI
IPRJ
IPRK
IPRL
IPRO
ABWCR
ASTCR
WCRH
WCRL
BCRH
BCRL
RAMER
MAR_0AH 16
MAR_0AL
Bit No.
8
8
8
8
8
16
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
Address *
H'FEA0
H'FEA1
H'FEA2
H'FEA4
H'FEA5
H'FEA6
H'FEA8
H'FEAA
H'FEB0
H'FEB1
H'FEC0
H'FEC1
H'FEC2
H'FEC3
H'FEC4
H'FEC5
H'FEC6
H'FEC7
H'FEC8
H'FEC9
H'FECA
H'FECB
H'FECE
H'FED0
H'FED1
H'FED2
H'FED3
H'FED4
H'FED5
H'FEDB
H'FEE0
H'FEE2
1
Module
TPU_5
TPU_5
TPU_5
TPU_5
TPU_5
TPU_5
TPU_5
TPU_5
TPU
TPU
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
BSC
BSC
BSC
BSC
BSC
BSC
FLASH
DMAC
DMAC
8
8
8
8
8
8
8
8
Data Bus
Width
8
8
8
8
8
16
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
16
Access
State
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2