MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 170
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MCF5272VF66R2J
Manufacturer Part Number
MCF5272VF66R2J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66R2J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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System Integration Module (SIM)
6.2.6
ALPR,
is activated by a write access with any data to ALPR followed by a STOP instruction.
The sequence to enter sleep mode is as follows:
Sleep mode is exited by an interrupt request from by either an external device or an on-chip peripheral as
detailed in
The sequence to enter stop mode is:
Stop mode is exited by an interrupt request from an external device as detailed in
6-10
1. Set power down and wakeup enable bits in the PMR as desired; set PMR[SLPEN].
2. Set the CPU interrupt priority level in the status register (SR). Interrupts below this level do not
3. Perform a write access with any data to ALPR.
4. Execute the STOP instruction. This must be the next instruction executed after the write to the
1. Set PMR[MOS]; clear PMR[SLPEN].
2. Set the CPU interrupt priority level in the status register (SR). Interrupts below this level do not
3. Perform a write access with any data to ALPR.
4. Execute the STOP instruction. This must be the next instruction executed after the write to the
reactivate the CPU. Note that any interrupt will cause the processor to exit low-power mode, but
only unmasked interrupts will cause the processor to resume operation.
ALPR.
reactivate the CPU.
ALPR.
Figure
Table
Interrupts, INT6–INT2
Interrupt, INT1
USART1, USART2
QSPI
USB
PLIC
General purpose I/O
Activate Low-Power Register (ALPR)
Address
6-6, is used to put the MCF5272 into a low power mode (sleep or stop). A low-power mode
Interrupt Source
Reset
Field
R/W
6-7.
MCF5272 ColdFire
15
Figure 6-6. Activate Low-Power Register (ALPR)
Table 6-7. Exiting Sleep and Stop Modes
Yes
Yes
Yes, interrupt and Rx signal change
Yes
Yes, interrupt and Rx signal change
Yes, interrupt
No
®
Integrated Microprocessor User’s Manual, Rev. 3
Exit Sleep
0000_0000_0000_0000
MBAR + 0x00E
Write only
ALPHR
Exit Stop USB Wake-on-Ring
Yes
Yes
No
No
No
No
No
Table
Yes
No
No
No
No
No
No
Freescale Semiconductor
6-7.
0
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