MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 280
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MCF5272VF66R2J
Manufacturer Part Number
MCF5272VF66R2J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66R2J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Universal Serial Bus (USB)
12.3.2.15 USB Endpoint 0 Interrupt Mask (EP0IMR) and General/Endpoint 0
Figure 12-18
Table 12-14
registers.
12-22
31–17
Bits
16
Reset
Reset
Reset
Reset
Field
Field
Field VEND_REQ FRM_MAT
Field OUT_EOT
Addr
R/W
R/W
R/W
R/W
DEV_CFG
lists field descriptions for the USB endpoint 0 interrupt mask and general/endpoint 0 interrupt
Interrupt Registers (EP0ISR)
shows the USB endpoint 0 interrupt mask and general/endpoint 0 interrupt registers.
Name
31
23
15
7
Interrupt bits are reset by writing a 1 to the specified bits. Writing 0 has no
effect.
—
MCF5272 ColdFire
OUT_EOP
Figure 12-18. USB Endpoint 0 Interrupt Mask (EP0IMR)
Reserved, should be cleared.
Device configuration change interrupt. Set when a device configuration change has been
received. The USB standard device requests SET_CONFIGURATION and SET_INTERFACE
generate a DEV_CFG interrupt. Any IN or OUT packets to the active endpoints cause a NAK
response to the host while this bit is set in order to allow the user to initialize the endpoints’
FIFO’s. Note that if one of these requests is done repeatedly and therefore the registers don’t
change, a DEV_CFG interrupt is still generated. If debug mode is enabled, a change in FAR also
generates an interrupt.
0 No interrupt pending
1 Device configuration change received
14
6
and General/Endpoint 0 Interrupt Registers (EP0ISR)
Table 12-14. EP0IMR and EP0ISR Field Descriptions
MBAR + 0x108C (EP0IMR); MBAR + 0x106C (EP0ISR)
OUT_LVL
ASOF
13
5
®
Integrated Microprocessor User’s Manual, Rev. 3
IN_EOT
SOF
—
12
NOTE
4
0000_0000
0000_0000
0000_0000
0000_0000
R/W
R/W
R/W
R/W
—
WAKE_CHG
IN_EOP
Description
11
3
RESUME
UNHALT
10
2
SUSPEND
HALT
17
9
1
Freescale Semiconductor
DEV_CFG
RESET
IN_LVL
24
16
8
0
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