MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 277
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MCF5272VF66R2J
Manufacturer Part Number
MCF5272VF66R2J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66R2J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
Bits
5–4
3–2
7
6
1
0
CRC_ERR
OUT_LVL
IN_DONE
IN_LVL
Name
—
—
MCF5272 ColdFire
CRC error generation enable. This bit enables CRC error generation for debug and test purpose.
In order to use this feature, the DEBUG bit must be set. Enabling this bit causes a CRC error on
the next data packet transmitted. The CRC_ERR bit must be set again in order to generate
another CRC error. This bit only applies to IN transfers. This command bit is write-only and always
returns 0 when read.
1 CRC error generation if DEBUG = 1
0 default value
Reserved, should be cleared.
Endpoint 0 OUT FIFO level for interrupt. This field selects the FIFO level to generate an OUT_LVL
interrupt. The OUT_LVL interrupt is generated when the FIFO fills above the selected level.
00 FIFO 25% Full
01 FIFO
10 FIFO
11 FIFO 100% Full
Endpoint 0 IN FIFO level for interrupt. This field selects the FIFO level to generate an IN_LVL
interrupt. The IN_LVL interrupt is generated when the FIFO falls below the selected level.
00 FIFO 25% Empty
01 FIFO
10 FIFO
11 FIFO 100% Empty
This bit controls the USB's response to IN tokens from the host. This bit is set at Reset and must
be cleared by software when the last byte of a transfer has been written to the IN-FIFO. This bit is
then subsequently set by the USB core when an end of transfer (EOT) event occurs indicating that
the transfer has been completed. An end of transfer (EOT) event is indicated by one of the
following:
a) An IN packet is transmitted that contains less than the maximum number of bytes defined at
b) A zero length IN packet is transmitted. This occurs when the previously transmitted IN packet
0 CPU has completed writing to the IN-FIFO and transfer is in progress. The USB module will
1 Transfer completed or CPU Busy writing transfer into the IN-FIFO. The USB module will only
Reserved, should be cleared.
send any amount of data in the FIFO or a zero-length packet when the FIFO is empty.
send maximum size packets or NAK responses if the FIFO contains less than a maximum size
packet. This bit is set at Reset and on an EOT event.
Table 12-12. EP0CTL Field Descriptions (continued)
endpoint configuration.
was full, and no more data remains in the IN-FIFO. Hence a single zero length packet must be
sent to indicate EOT.
50%
75%
50%
75%
Full
Empty
Full
Empty
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
Universal Serial Bus (USB)
12-19
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