MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 364
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MCF5272VF66R2J
Manufacturer Part Number
MCF5272VF66R2J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66R2J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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UART Modules
1
2
3
16.3.1
The UART mode registers 1 (UMR1n) control configuration. UMR1n can be read or written when the
mode register pointer points to it, at RESET or after a
UCRn[MISC]. After UMR1n is read or written, the pointer points to UMR2n.
Table 16-2
16-4
UART0
0x12C
0x13C
0x130
0x134
0x138
UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset command. That
is, if channel operation is not disabled, undesirable results may occur.
This address is for factory testing. Reading this location results in undesired effects and possible incorrect transmission or
reception of characters. Register contents may also be changed.
Address-triggered commands
MBAR Offset
Address
Reset
Field
R/W
UART1
0x16C
0x17C
0x170
0x174
0x178
describes UMR1n fields.
UART Mode Registers 1 (UMR1n)
MBAR + 0x100 (UART0), 0x140 (UART1). After UMR1n is read or written, the pointer points to UMR2n.
RxRTS
UART registers are accessible only as bytes.
UART Receiver FIFO
registers—(URFn) [p. 16-4]
UART Fractional Precision
Divider Control registers
(UFPDn) [p. 16-17]
(Read) UART input port
registers—(UIPn) [p. 16-17]
(Write) Do not access.
(Read) Do not access.
(Write) UART output port bit
set command
registers—(UOP1n
16-18]
(Read) Do not access.
(Write) UART output port bit
reset command
registers—(UOP0n
16-18]
7
MCF5272 ColdFire
RxIRQ/FFULL
Table 16-1. UART Module Programming Model (continued)
[31:24]
6
Figure 16-2. UART Mode Registers 1 (UMR1n)
3
3
) [p.
) [p.
2
2
2
®
ERR
Integrated Microprocessor User’s Manual, Rev. 3
5
NOTE
[23:16]
4
0000_0000
RESET MODE REGISTER POINTER
R/W
PM
3
[15:8]
—
—
—
—
—
—
—
—
PT
2
Freescale Semiconductor
1
command using
B/C
[7:0]
0
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