MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 217

• Manufacturer Part Number: MCF5272VF66R2J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VF66R2J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

10.3.3
The DSAR provides a 32-bit address, which the DMA controller drives onto the internal address bus for
all of the channel’s read accesses. The address value is altered after each read access according to the
addressing mode.
Freescale Semiconductor
Bits
Reset
4
3
2
1
0
Field
Addr
R/W
Name
ASC
31
INV
TE
TC
—
DMA Source Address Register (DSAR)
Invalid combination.
0 No invalid combination detected.
1 An invalid combination of request and address modes is programmed into the mode register. INV
Address sequence complete.
0 Address sequence is not complete.
1 The address sequence is complete. This occurs when the byte counter decrements to 0. Corresponds
Reserved, should be cleared.
Transfer error.
0 No transfer error.
1 A DMA data transfer terminated with an error such as an internally generated bus error. This generally
Transfer complete.
1 A data transfer completed successful. The bit is cleared when DMA module is reset. Writing a 0 to this
remains set until it is cleared by writing a 1 to it or by a hardware reset. Writing a 0 has no effect. No
further transfers can take place when this bit is set.
to DMA complete. ASC remains set until it is cleared by writing a 1 to its location or by a hardware reset.
Writing a 0 has no effect. No further transfers can take place when ASC is set. It is important to ensure
that the combination of source address, destination address, and transfer sizes ensures that the byte
counter always decrements to 0.
occurs when the address is not decoded successfully by an on-chip peripheral or by a chip select
register. TE remains set until it is cleared by writing a 1 to its location or by a hardware reset. Writing 0
has no effect. No further transfers can take place when TE is set.
location has no effect. This bit is available to show that the DMA transfers have started. Otherwise it is
not essential to monitor the status of this bit.
MCF5272 ColdFire
Figure 10-3. DMA Source Address Register (DSAR)
Table 10-3. DIR Field Descriptions (continued)
0000_0000_0000_0000_0000_0000_0000_0000
®
Integrated Microprocessor User’s Manual, Rev. 3
MBAR + 0x00EC
SRCADR
R/W
Description
DMA Controller
0
10-5