MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 302
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MCF5272VF66R2J
Manufacturer Part Number
MCF5272VF66R2J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66R2J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Physical Layer Interface Controller (PLIC)
13.2.3.2
When the incoming B channels contain HDLC encoded data they are presented on the physical line least
significant bit (lsb) first. The Soft HDLC expects the first bit received to be aligned in the lsb position of
a byte, with the last bit received aligned in the msb position.
Because the presentation of HDLC encoded data on the physical interface is lsb (least significant bit) first
for B1 and B2 the lsb is right-aligned in the transmit and receive shift register, that is, the first bit of the
B-channel received is aligned in the lsb position through to the last received bit of a byte that is aligned in
the msb position.
The ordering of the bytes over four frames within the longword register is as for unencoded data; that is,
the first frame is aligned in the MSB through to the fourth frame, which is aligned in the LSB position. See
Figure
13.2.3.3
When the incoming D channels contain HDLC-encoded data, they are presented on the physical line lsb
first. The Soft HDLC expects the first bit received to be aligned in the lsb position of a byte, with the last
bit received aligned in the msb position.
13-6
.
Unencoded
32-bit B1/B2 Receive/Transmit Registers, PnB1RR, PnB2RR, PnB1TR, PnB2TR
HDLC
Encoded
Din/Dout
Din/Dout
13-6.
B
7
DCL
FSR
B
6
B-Channel HDLC Encoded Data
D-Channel HDLC Encoded Data
B
5
Frame 0
B
4
B
B
B
3
7
0
MCF5272 ColdFire
B
Figure 13-6. B-Channel Unencoded and HDLC Encoded Data
B
B
2
6
1
B
B
B
1
5
2
B
B
B
4
3
0
B 1
B
B
B
3
4
7
B
B
B
2
5
6
B
B
B
1
6
5
®
Frame 1
B
B
B
Integrated Microprocessor User’s Manual, Rev. 3
0
7
Frame 0
4
B
B
B
7
0
3
B
B
6
1
B
2
B
B
2
5
B
B
B
1
4
3
B 2
B
B
B
0
4
3
B
B
B
7
2
5
B
B
B
6
6
1
B
B
B
5
7
0
Frame 2
D
D
B
0
0
4
D
D
D
B
1
1
3
B
2
B
1
B
0
B
7
B
6
B
Frame 3
5
Freescale Semiconductor
B
B
7
0
B
4
B
B
6
1
Frame 1
B
B
B
3
5
2
B
B
B
2
4
3
B
B
B
1
3
4
B
B
B
0
2
5
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