MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 39
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MCF5272VF66R2J
Manufacturer Part Number
MCF5272VF66R2J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66R2J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MCF5272 ColdFire
Microprocessor
User’s Manual
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Document Revision History
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Freescale Semiconductor
Rev. No.
http://www.freescale.com/
2.1
3
Updated to meet Freescale identity guidelines.
• Formatting, layout, spelling, and grammar corrections.
• Corrected the TxFIFO bit description In
• Corrected
• Corrected
• Corrected
• Corrected
MCF5272 ColdFire
UTBn”, is “After being set, this bit is cleared by writing UTBn”).
second SDCLK clock cycle).
asserting on the second SDCLK clock cycle).
second SDCLK clock cycle).
asserting on the second SDCLK clock cycle).
Figure 20-12
Figure 20-16
Figure 20-13
Figure 20-17
®
Integrated Microprocessor User’s Manual, Rev. 3
(OE signal was asserting on the third SDCLK clock cycle, is asserting on the
(OE signal was asserting on the third SDCLK clock cycle, is asserting on the
(R/W and BS signals were asserting on the third SDCLK clock cycle, are
(R/W and BS signals were asserting on the third SDCLK clock cycle, are
®
Integrated
Substantive Change(s)
Table 16-9
(was “Once set, this bit is cleared by reading
xxxix
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