MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 317
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MCF5272VF66R2J
Manufacturer Part Number
MCF5272VF66R2J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66R2J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
14–12
Bits
7–6
15
11
10
9
8
5
4
3
2
1
0
B2RIE
B1RIE
Name
B2TIE
B1TIE
GMR
DTIE
DRIE
GCR
GMT
GCT
—
—
IE
Interrupt enable. Allows the port to generate interrupts to the CPU. When cleared, the IE bit masks all
periodic and aperiodic interrupts associated with the respective port.
Reserved, should be cleared.
Interrupt enable for the C/I channel receive.
0 Interrupt masked
1 Interrupt enabled. When set, an interrupt is enabled which occurs when the corresponding GCR
C/I channel transmit Interrupt enable.
0 Interrupt masked
1 Interrupt enabled.
Interrupt enable for the monitor channel receive.
0 Interrupt masked
1 Interrupt enabled.
Interrupt enable for the monitor channel transmit.
0 Interrupt masked
1 Interrupt enabled.
Reserved, should be cleared.
D transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled.Interrupt occurs when the corresponding PnPSR[DTDE] or PnPSR[DTUE] is set.
B2 transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B2TDE] or PnPSR[B2TUE] is
B1 transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B1TDE] or PnPSR[B1TUE] is
D receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[DRDF] or PnPSR[DROE] is
B2 receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B2RDF] or PnPSR[B2ROE] is
B1 receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled.Interrupt occurs when the corresponding PnPSR[B1RDF] or PnPSR[B1ROE] is
MCF5272 ColdFire
status bit is set.
set.
set.
set.
set.
set.
Table 13-4. P0ICR–P3ICR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
Physical Layer Interface Controller (PLIC)
13-21
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