MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 229

• Manufacturer Part Number: MCF5272VF66R2J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VF66R2J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

11.5.1
The ECR register,
system reset.
Freescale Semiconductor
31–26
24–2
Bits
25
1
0
Reset
Reset
Field
Field
Addr
R/W
R/W
ETHER_EN
Ethernet Control Register (ECR)
RESET
TX_RT
Name
—
—
31
15
Figure
MCF5272 ColdFire
Reserved, should be cleared.
Transmit retime.
0 Normal operation, seven-wire serial mode.
1 The transmit output signals (E_TxD[3:0], E_TxEN, and E_TxER) are delayed by one-half of a
Reserved, should be cleared.
Ethernet enable. When this bit is set, the FEC is enabled, and reception and transmission is possible.
When this bit is cleared, reception is immediately stopped and transmission is stopped after a bad
CRC is appended to any frame currently being transmitted. The buffer descriptor(s) for an aborted
transmit frame are not updated following deassertion of ETHER_EN. When ETHER_EN is
deasserted, the DMA, buffer descriptor, and FIFO control logic are reset, including FIFO pointers.
Ethernet controller reset. When this bit is set, the equivalent of a hardware reset is performed but it
is local to the FEC. ETHER_EN is cleared and all other FEC registers take their reset values. Also,
any transmission/reception currently in progress is abruptly aborted. This bit is automatically cleared
by hardware once the reset sequence is complete (approximately 16 clock cycles after being set).
E_TxCLK period. This bit should be set to provide compatibility with transceivers that have hold
time requirements that exceed the MII specification.
11-5, is used to enable/disable the FEC. It is written by the user and cleared at
—
Figure 11-5. Ethernet Control Register (ECR)
Table 11-7. ECR Field Descriptions
®
26
Integrated Microprocessor User’s Manual, Rev. 3
TX_RT
25
—
0000_0000_0000_0000
0000_0000_0000_0000
24
MBAR + 0x840
Read/write
Read/write
Description
—
2
ETHER_EN RESET
1
Ethernet Module
16
0
11-11