MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 224
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MCF5272VF66R2J
Manufacturer Part Number
MCF5272VF66R2J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66R2J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Ethernet Module
As soon as a collision window (512 bits) of data is received, and if address recognition has not rejected the
frame, the FEC starts transferring the incoming frame to the receive buffer descriptor’s (RxBD’s)
associated data buffer. If the frame is a runt (due to collision) or is rejected by address recognition, no
receive buffers are filled. Thus, no collision frames are presented to the user except late collisions, which
indicate serious LAN problems. When the data buffer has been filled, the FEC clears RxBD[E] and
generates an RXB interrupt (if RBIEN is asserted in EIMR register). If the incoming frame exceeds the
length of the data buffer, the FEC fetches the next RxBD in the table and, if it is empty, continues
transferring the rest of the frame to this BD’s associated data buffer.
The RxBD length is determined in the R_BUFF_SIZE value in the EMRBR register. The user should
program R_BUFF_SIZE to be at least 128 bytes. R_BUFF_SIZE must be quad-word (16-byte) aligned.
During reception, the FEC checks for a frame that is either too short or too long. When the frame ends
(carrier sense is negated), the receive CRC field is checked and written to the data buffer. The data length
written to the last BD in the Ethernet frame is the length of the entire frame. Frames shorter than 64 bytes
are discarded automatically with no system bus impact.
When the receive frame is complete, the FEC sets RxBD[L], writes the other frame status bits into the
RxBD and clears RxBD[E]. The FEC next generates a maskable interrupt (EIR[RFINT], maskable by
EIMR[RFIEN]), indicating that a frame has been received and is in memory. The FEC then waits for a new
frame. The FEC receives serial data lsb first.
11.4.2
In addition to the FEC address recognition logic, an external CAM may be used for frame reject with no
additional pins other than those in the MII interface. This CAM interface is documented in an application
note titled “Using Freescale’s Fast Static RAM CAMs with the MPC860T’s Media Independent Interface,”
located at the following URL: http://www.freescale.com.
11.4.3
The FEC filters the received frames based on the type of destination media access controller address
(hardware address). There are three destination address (DA) types:
The difference between an individual address and a group address is determined by the I/G bit in the
destination address field. A flowchart for address recognition on received frames is illustrated in
Figure 11-4
11-6
•
•
•
•
•
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes
may occur, but if a 00 bit sequence is detected before the SFD byte, the frame is ignored.
After the first 8 bytes of the frame have been passed to the receive FIFO, the FEC performs address
recognition on the frame.
Individual (unicast)
Group (multicast)
Broadcast (all-ones group address)
CAM Interface
Ethernet Address Recognition
and summarized in
MCF5272 ColdFire
Table
11-3.
®
Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
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