MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 535

• Manufacturer Part Number: MCF5272VF66R2J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VF66R2J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

Q
QSPI
R
RAM
RAM base address registers,
RAMBAR
Read/write, bus,
Registers
Freescale Semiconductor
programming model,
width register,
address register,
baud rate selection,
command RAM bit description,
data register,
delay register,
interrupt,
mode register,
module description,
operation,
overview and features,
programming
RAM
slave bus interface,
transfer
wrap register,
QSPI command bit description,
USB configuration, 12-28,
overview,
power management programming,
A0–A6,
A7,
AATR,
ABLR/ABHR, 5-6,
access control, 2-9,
activate low-power,
address,
address (A0 – A6),
ALPR,
B2 data transmit,
BI data receive,
cache configuration,
cache control,
example,
model,
command,
model,
receive,
transmit,
data,
delays,
length,
2-5
6-10
14-8
5-7
2-5
2-5
14-13
14-9
14-4
14-8
14-7
4-3
14-3
14-5
14-6
14-16
14-6
14-14
14-12
20-2
4-12
14-11
14-9
18-4
13-15
14-14
13-17
2-5
14-3
4-14
14-6
5-9
14-1
6-10
2-9
18-2
14-1
MCF5272 ColdFire
2-9
12-30
14-15
14-15
4-4
®
Integrated Microprocessor User’s Manual, Rev. 3
CACR,
CCR,
chip select
condition code, 2-6,
condition code (CCR),
CSBR,
CSOR,
CSR,
D data receive,
D0–D7,
data,
data breakpoint/mask,
data D0 - D7,
DBCR,
D-Channel request,
DDAR,
debug attribute trigger,
descriptor active,
device identification,
DIR,
DMA
DMR,
DSAR,
Ethernet control,
FIFO
GCI
GPIO
hash table
IDCODE,
integer data formats in,
interrupt
interrupt controller
base,
general,
option,
byte count,
controller,
destination address,
interrupt,
mode,
sourse address,
receive bound,
receive start,
transmit start,
C/I channel transmit status,
monitor channel transmit abort,
control port,
data,
data direction,
high,
low,
event,
mask,
vector status,
pending and mask, 7-5,
2-5
10-4
5-10
2-6
10-2
11-29
8-3
17-11
8-5
8-3
10-5
11-28
2-9
10-6
10-6
2-5
11-13
11-12
10-2
8-5
6-11
8-2
10-4
10-2
10-6
2-5
17-2–17-8
13-16
11-20
11-14
11-22
17-10
11-11
11-19
11-15
10-5
13-32
2-6
6-11
5-12
10-6
2-6
5-7
2-10
7-5
13-30
13-26
Index-5
Index