MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 441
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MCF5272VF66R2J
Manufacturer Part Number
MCF5272VF66R2J
Description
IC MCU 166MHZ 196MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272VF66R2J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5272VF66R2J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Signal Descriptions
19.16 Physical Layer Interface Controller TDM Ports and UART 1
The MCF5272 has four dedicated physical layer interface ports for connecting to external ISDN
transceivers, CODECs and other peripherals. There are three sets of pins for these interfaces. Port 0 has its
own dedicated set of pins. Ports 1, 2, and 3 share a set of pins. Port 3 can also be configured to use a
dedicated pin set. Ports 1, 2, and 3 always share the same data clock (DCL).
19.16.1 GCI/IDL TDM Port 0.
This section describes signals used by the PLIC module port 0 interface.
19.16.1.1 Frame Sync (FSR0/FSC0/PA8)
IDL mode: FSR0 is an input for the 8-KHz frame sync for port 0.
GCI mode: FSC0 is an input for the 8-KHz frame sync for port 0. It is active high in this mode. Normally
the GCI FSC signal is two clocks wide and is aligned with the first B-channel bit of the GCI frame. Many
U-interface devices including the MC145572 and MC145576 change the width of FSC to one clock every
12 mS. This indicates U-interface super frame boundary.
Port A mode: This pin can be independently configured as PA8.
19.16.1.2 D-Channel Grant (DGNT0/PA9)
IDL mode: This pin can be independently configured as the input, DGNT0, used by a layer-one ISDN S/T
transceiver to indicate that D-channel access has been granted.
Port A mode: This pin can be independently configured as I/O pin PA9.
19.16.1.3 Data Clock (DCL0/URT1_CLK)
IDL mode: This pin is the clock used to clock data in and out of DIN0 and DOUT0 for IDL port 0. Data
is clocked into DIN0 on the falling edge and clocked out of DOUT0 on the rising edge of DCL0.
GCI mode: This pin is used to clock data in and out of DIN0 and DOUT0 for GCI port 0. DCL0 is twice
the bit rate (two clocks per data bit).
UART1: URT1_CLK provides a clock input which can be the baud rate clock.
19.16.1.4 Serial Data Input (DIN0/URT1_RxD)
IDL mode: The DIN0 input is for clocking data into IDL port 0. Data is clocked into DIN0 on the falling
edge of DCL0.
GCI mode: The DIN0 input is for clocking data into GCI port 0. DCL0 is twice the bit rate (two clocks per
data bit).
UART1: URT1_RxD is the receiver serial data input for the UART1 module. Data received on this pin is
sampled on the rising edge of the serial clock source with the least significant bit first. When the UART1
clock is stopped for power-down mode, any transition on this pin restarts it.
®
MCF5272 ColdFire
Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
19-31
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