MCF5272VF66R2J Freescale Semiconductor, MCF5272VF66R2J Datasheet - Page 473

• Manufacturer Part Number: MCF5272VF66R2J
• Description: IC MCU 166MHZ 196MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VF66R2J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No

20.12.4 Soft Reset Operation
If the soft reset bit, SCR[SOFTRST], is programmed to generate a reset, RSTO is asserted for 128 clocks,
resetting all external devices as with a normal or master reset. All internal peripherals with the exception
of the SIM, chip select, interrupt controller, GPIO module, and SDRAM controller are reset also. The
SDRAM controller is reset only when DRESETEN is tied low.
SCR[SOFTRST] is automatically cleared at the end of the 128 clock period. Software can monitor this bit
to determine the end of the soft reset.
SCR[SOFTRST].
During the soft reset period, all bus signals continue to operate normally.
Freescale Semiconductor
CLKIN
SoftRST
RSTO
INTERNAL
PERIPHERALS
RSTI
The levels of the mode pins are not sampled during a software watchdog
reset. If the port size and acknowledge features of CS0 are different from the
values programmed in CSBR0 and CSOR0 at the time of the software
watchdog reset, you must assert RSTI during software watchdog reset to
cause the mode pins to be resampled.
Like the normal reset, the soft reset does not reset the SDRAM controller
unless DRESETEN is asserted during the reset. When DRESETEN is
negated, SDRAM refreshes continue to be generated during and after reset
at the programmed rate and with the programmed waveform timing.
MCF5272 ColdFire
Figure 20-24. Soft Reset Timing
Figure 20-24
®
Integrated Microprocessor User’s Manual, Rev. 3
NOTE
NOTE
shows the timing of RSTO when asserted by
CLK CYCLES
T = 128
Bus Operation
20-25