HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 1038

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 32 Electrical Characteristics
32.3.10 LCDC Timing
Table 32.13 LCDC Timing
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Item
LCLK input clock frequency
LCLK input clock rise time
LCLK input clock fall time
LCLK input clock duty
Clock (CL2/DCLK) cycle time
Clock (CL2/DCLK) high-level width
Clock (CL2/DCLK) low-level width
Clock (CL2/DCLK) transition time
(rise, fall)
Data (LCD) delay time
Data (LCD) transition time (rise, fall)
Display enable (M/DISP) delay time
Display enable (M/DISP) transition
time (rise, fall)
Horizontal sync. signal (CL1/Hsync)
delay time
Horizontal sync. singal (CL1/Hsync)
transition time
Vertical sync. signal (FLM/Vsync)
delay time
Vertical sync. signal (FLM/Vsync)
transition time
Rev.6.00 Mar. 27, 2009 Page 980 of 1036
REJ09B0254-0600
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
FREQ
R
F
DUTY
CC
CHW
CLW
CT
DD
DT
ID
IT
HD
HT
VD
VT
Min
—
—
—
90
25
7
7
—
–3.5
—
–3.5
—
–3.5
—
–3.5
—
Max
50
3
3
110
—
—
—
3
3
3
3
3
3
3
3
3
Unit
MHz
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
32.51