HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 114

IC SH MPU ROMLESS 240BGA

HD6417727BP160CV

Manufacturer Part Number
HD6417727BP160CV
Description
IC SH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727BP160CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Package
240CSP
Family Name
SuperH
Maximum Speed
160 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
104
Interface Type
SCI/USB
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Price
Part Number:
HD6417727BP160CV
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Part Number:
HD6417727BP160CV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 2 CPU
Instruction Format
nm type
15
md type
15
nd4 type
15
nmd type
15
Rev.6.00 Mar. 27, 2009 Page 56 of 1036
REJ09B0254-0600
xxxx
xxxx
xxxx
xxxx
nnnn
xxxx
nnnn
xxxx
mmmm
mmmm
mmmm
nnnn
dddd
dddd
dddd
xxxx
0
0
0
0
Source
Operand
mmmm: register
direct
mmmm: register
indirect
mmmm: post-
increment register
indirect (multiply-
and-accumulate
operation)
nnnn: * post-
increment register
indirect (multiply-
and-accumulate
operation)
mmmm: post-
increment
register indirect
mmmm: register
direct
mmmm: register
direct
mmmmdddd:
register indirect
with displacement
R0 (register
direct)
mmmm: register
direct
mmmmdddd:
register indirect
with displacement
Destination
Operand
nnnn: register
direct
nnnn: register
indirect
MACH, MACL
nnnn: register
direct
nnnn: pre-
decrement register
indirect
nnnn: indexed
register indirect
R0 (register direct) MOV.B @(disp,Rm),R0
nnnndddd:
register indirect
with displacement
nnnndddd:
register indirect
with displacement
nnnn: register
direct
Sample Instruction
ADD
MOV.L Rm,@Rn
MAC.W @Rm+,@Rn+
MOV.L @Rm+,Rn
MOV.L Rm,@-Rn
MOV.L Rm,@(R0,Rn)
MOV.B R0,@(disp,Rn)
MOV.L Rm,@(disp,Rn)
MOV.L @(disp,Rm),Rn
Rm,Rn

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