HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 440

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Direct Memory Access Controller (DMAC)
14.1.3
Table 14.1 shows the DMAC pins.
Table 14.1 Pin Configuration
Channel
0
14.1.4
Table 14.2 summarizes the DMAC registers. DMAC has a total of 18 registers, four registers for
each channel and two registers for controlling all channels.
Table 14.2 DMAC Registers
Channel
0
1
Rev.6.00 Mar. 27, 2009 Page 382 of 1036
REJ09B0254-0600
Pin Configuration
Register Configuration
Name
DMA source address
register 0
DMA destination address
register 0
DMA transfer count
register 0
DMA channel control
register 0
DMA source address
register 1
DMA destination address
register 1
DMA transfer count
register 1
DMA channel control
register 1
Name
DMA transfer request
DREQ acknowledge
DMA request
acknowledge
Abbrevi-
ation
SAR0
DAR0
DMATCR0 R/W
CHCR0
SAR1
DAR1
DMATCR1 R/W
CHCR1
Symbol
DREQ0
DACK0
DRAK0
R/W
R/W
R/W
R/W *
R/W
R/W
R/W *
I/O
Input
Output
Output
1
1
Initial
Value
Undefined
Undefined
Undefined
H'00000000 H'0400002C
Undefined
Undefined
Undefined
H'00000000 H'0400003C
Function
DMA transfer request input from external
device to channel 0
Strobe output to an external I/O at DMA
transfer request from external device to
channel 0
Output showing that DREQ0 has been
accepted
Address
H'04000020
(H'A4000020) *
H'04000024
(H'A4000024) *
H'04000028
(H'A4000028) *
(H'A400002C) *
H'04000030
(H'A4000030) *
H'04000034
(H'A4000034) *
H'04000038
(H'A4000038) *
(H'A400003C) *
4
4
4
4
4
4
4
4
Register
Size
32 bits
32 bits
24 bits
32 bits
32 bits
32 bits
24 bits
32 bits
Access
Size
16, 32 *
16, 32 *
16, 32 *
8, 16, 32 *
16, 32 *
16, 32 *
16, 32 *
8, 16, 32 *
2
2
3
2
2
3
2
2