HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 197
HD6417727BP160CV
Manufacturer Part Number
HD6417727BP160CV
Description
IC SH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP160CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Package
240CSP
Family Name
SuperH
Maximum Speed
160 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
104
Interface Type
SCI/USB
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417727BP160CV
Manufacturer:
LITEON
Quantity:
46 000
Company:
Part Number:
HD6417727BP160CV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 197 of 1098
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4.4
4.4.1
The reset sequence is used to power up or restart the SH7727 from the initialization state. The
RESETP and RESETM signals are sampled every clock cycle, and in the case of a power-on reset,
all processing being executed (excluding the RTC) is suspended, all unfinished events are
canceled, and reset processing is executed immediately. In the case of a manual reset, however,
processing to retain external memory contents is continued. The reset sequence consists of the
following operations:
1. The MD bit in SR is set to 1 to place the SH7727 in privileged mode.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except NMI interrupt when
3. The RB bit in SR is set to 1.
4. An encoded value of H'000 in a power-on reset or H'020 in a manual reset is written to bits 11
5. Instruction execution jumps to the user-written exception handler at address H'A0000000.
4.4.2
An interrupt processing request is accepted on completion of the current instruction. The interrupt
acceptance sequence consists of the following operations:
1. The contents of the PC and SR are saved in SPC and SSR, respectively.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except NMI interrupt when
3. The MD bit in SR is set to 1 to place the SH7727 in privileged mode.
4. The RB bit in SR is set to 1.
5. An encoded value identifying the exception event is written to bits 11 to 0 of the INTEVT and
0:
imm:
EXPEVT register, INTEVT and INTEVT2 registers
31
0
BLMSK bit is 1).
to 0 of the EXPEVT register to identify the exception event.
BLMSK bit is 1).
INTEVT2 registers.
Figure 4.3 Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers
Reserved bits, always read as zero
8-bit immediate data in TRAPA instruction
Exception Handling Operation
Reset
Interrupts
0 Exception code
11
0
TRA register
31
0
Rev.6.00 Mar. 27, 2009 Page 139 of 1036
Section 4 Exception Handling
REJ09B0254-0600
0
9
imm
2 0
00
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