HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 143

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The correspondence between DSP data transfer operands and registers is shown in table 2.29.
CPU core registers are used as a pointer address that indicates a memory address.
Table 2.29 Correspondence between DSP Data Transfer Operands and Registers
CPU
register
DSP
register
2.6.4
DSP operation instructions are instructions for digital signal processing performed by the DSP
unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed
in parallel. The instruction code is divided into an A field and B field; a parallel data transfer
instruction is specified in the A field, and a single or double data operation instruction in the B
field. Instructions can be specified independently, and are also executed independently. The
parallel data transfer instruction specified in the A field is exactly the same as a double data
transfer instruction. The function of the A field—that is, the data transfer instruction field—is
Register
DSP Operation Instruction Set
R0
R1
R2 (As2)
R3 (As3)
R4 (Ax0)
R5 (Ax1)
R6 (Ay0)
R7 (Ay1)
R8 (Ix)
R9 (Iy)
A0
A1
M0
M1
X0
X1
Y0
Y1
A0G
A1G
Yes
Yes
Ax
Yes
Ix
Yes
Yes
Dx
Yes
Yes
Ay
Rev.6.00 Mar. 27, 2009 Page 85 of 1036
Yes
Iy
Yes
Yes
Dy
Yes
Yes
Da
REJ09B0254-0600
Section 2 CPU
Yes
Yes
Yes
Yes
As
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Ds