HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 472

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Direct Memory Access Controller (DMAC)
Bus Modes: There are two types of bus modes, cycle steal mode and burst mode. Select the mode
in the TM bits in CHCR0 to CHCR3.
• Cycle-Steal Mode
In the cycle-steal mode, the bus right is moved to another bus master after one transfer unit (byte,
word, longword, or 16-byte unit) of DMA transfer. If another transfer request occurs after the bus
right moving, the bus right are re-moved to the DMAC. Then, the DMAC performs transfer for
one transfer unit and releases the bus right again. This operation is repeated until the transfer end
condition is satisfied.
In the cycle-steal mode, transfer areas are not affected by settings of the transfer request source,
transfer source, and transfer destination. Figure 14.14 shows an example of the DMA transfer
timing in the cycle steal mode. In this example, the following conditions are set:
Rev.6.00 Mar. 27, 2009 Page 414 of 1036
REJ09B0254-0600
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Dual address mode
DREQ level detection
(External Memory Space (Ordinary Memory) → External Device with DACK)
Figure 14.13 Example of DMA Transfer Timing in Single Address Mode
D31 to D0
A25 to A0
DACKn
CKIO
WEn
CSn
RD
source address
Transfer
+4
+8
+12