HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 191

IC SH MPU ROMLESS 240BGA

HD6417727BP160CV

Manufacturer Part Number
HD6417727BP160CV
Description
IC SH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727BP160CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Package
240CSP
Family Name
SuperH
Maximum Speed
160 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
104
Interface Type
SCI/USB
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417727BP160CV
Manufacturer:
LITEON
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46 000
Part Number:
HD6417727BP160CV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 4.2
Exception
Type
Reset
General
exception
events
Current
Instruction
Aborted
Aborted
and retried
Completed
Exception Event Vectors
Exception Event
Power-on reset
Manual reset
H-UDI reset
CPU address error
(instruction access)
TLB miss
(instruction access
not in repeat loop)
TLB miss
(instruction access in
repeat loop) *
TLB invalid
(instruction access)
TLB protection
violation
(instruction access)
General illegal
instruction exception
Illegal slot instruction
exception
CPU address error
(data access)
TLB miss
(data access not in
repeat loop)
TLB miss
(data access in repeat
loop) *
TLB invalid (data
access)
TLB protection
violation
(data access)
Initial page write
Unconditional trap
(TRAPA instruction)
User breakpoint trap
DMA address error
4
4
Priority *
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
Rev.6.00 Mar. 27, 2009 Page 133 of 1036
10
12
Exception
Order
1
2
2
3
4
5
5
6
7
7
8
9
5
n *
2
Section 4 Exception Handling
Vector
Address
H'A0000000
H'A0000000
H’A0000000
REJ09B0254-0600
Vector Offset
H'00000100
H'00000400
H’00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000400
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100

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