HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 704

• Manufacturer Part Number: HD6417727BP160CV
• Description: IC SH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP160CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Package: 240CSP
• Family Name: SuperH
• Maximum Speed: 160 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 104
• Interface Type: SCI/USB
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 20 Serial IO (SIOF)
20.3.8
SIOF has the following four types of interrupt. These types are reflected to IRR4 register in
interrupt controller (INTC).
• Transmit interrupt (TXI)
• Receive interrupt (RXI)
• Control interrupt (CCI)
• Error interrupt (ERI)
(1) Interrupt Factor
Each interrupt is submitted by its multiple factors. Each factor is shown in SIOF register as SIOF
states. Table 20.12 shows SIOF interrupt factors.
Table 20.12 SIOF Interrupt Factors
No.
1
2
3
4
5
6
7
8
9
10
11
Rev.6.00 Mar. 27, 2009 Page 646 of 1036
REJ09B0254-0600
Type
Transmit
(TXI)
Receive
(RXI)
Control
(CCI)
Error
(ERI)
Interrupt
Bit
TDREQ
RDREQ
TCRDY
RCRDY
TFEMP
RFFUL
TFUDF
TFOVF
RFOVF
RFUDF
FSERR
Function
Transmit FIFO send request
Receive FIFO send request
Transmit control data ready
Receive control data ready
Transmit FIFO empty
Receive FIFO full
Transmit FIFO under flow
Transmit FIFO over flow
Receive FIFO over flow
Receive FIFO under flow
F3 error
Explanation of Interrupt
Data of over setting is stared to
transmit FIFO
Data of over setting is stared to
receive FIFO
Enable writing into transmit
control data register
Valid data is stored in receive
control data register
Transmit FIFO is empty
Receive FIFO is full
The serial data send timing
comes when transmit FIFO is
empty
Write to transit FIFO when
transmit FIFO is full
Receive serial data when
receive FIFO is full
Read receive FIFO when
receive FIFO is empty
Serial signal is received before
setting bit number (at slave)