HD6417727BP160CV Renesas Electronics America, HD6417727BP160CV Datasheet - Page 217
HD6417727BP160CV
Manufacturer Part Number
HD6417727BP160CV
Description
IC SH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP160CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
160MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Package
240CSP
Family Name
SuperH
Maximum Speed
160 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
104
Interface Type
SCI/USB
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417727BP160CV
Manufacturer:
LITEON
Quantity:
46 000
Company:
Part Number:
HD6417727BP160CV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 217 of 1098
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Specify the entry address for selecting the entry (bits 11 to 4), L indicating the longword position
within the (16-byte) line (bits 3 and 2: 00 is longword 0, 01 is longword 1, 10 is longword 2, and
11 is longword 3), W for selecting the way (bits 12 and 11: in normal mode, 00 is way 0, 01 is
way 1, 10 is way 2, and 11 is way 3), and H'F1 to indicate data array access (bits 31 to 24).
Both reading and writing use the longword of the data array specified by the entry address, way
number and longword address. The access size of the data array is fixed at longword.
1. Address array access
2. Data array access (both read and write accesses)
X: 0 for read, don't care for write
*: Don't care bit
Address specification
Address specification
Data specification
Data specification
Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access
Read access
Write access
0 0 0
31
31
31 30 29
31
31
1111 0000
1111 0000
1111 0001
24
24
24
Address tag (31−10)
23
23
23
* ………… *
* ………… *
* ………… *
14
14
14
13
13
13
Longword
W
W
W
12
12
12
11
11
10
11
Rev.6.00 Mar. 27, 2009 Page 159 of 1036
Entry
Entry
Entry
9
LRU
4
4
4
4
3
3
3
3
A
0
X
L
REJ09B0254-0600
X
2
*
2
*
2
Section 5 Cache
2
1
0
0
0
1
U
0
0
0
V
0
0
0
0
0
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