MC68HC916Y3CFT16 Freescale Semiconductor, MC68HC916Y3CFT16 Datasheet - Page 115

• Manufacturer Part Number: MC68HC916Y3CFT16
• Description: IC MCU 96K FLASH 16MHZ 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC916Y3CFT16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MC68HC16Y3/916Y3
USER’S MANUAL
1. MAINTAIN LOW LEAKAGE ON THE XFC NODE. REFER TO APPENDIX A ELECTRICAL CHARACTERISTICS FOR MORE INFORMATION.
2. RECOMMENDED LOOP FILTER FOR REDUCED SENSITIVITY TO LOW FREQUENCY NOISE.
A voltage controlled oscillator (VCO) in the PLL generates the system clock signal. To
maintain a 50% clock duty cycle, the VCO frequency (f
the system clock frequency, depending on the state of the X bit in SYNCR. The clock
signal is fed back to a divider/counter. The divider controls the frequency of one input
to a phase comparator. The other phase comparator input is a reference signal, either
from the crystal oscillator or from an external source. The comparator generates a con-
trol signal proportional to the difference in phase between the two inputs. This signal
is low-pass filtered and used to correct the VCO output frequency.
Filter circuit implementation can vary, depending upon the external environment and
required clock stability. Figure 5-5 shows two recommended system clock filter net-
works. XFC pin leakage must be kept as low as possible to maintain optimum stability
and PLL performance.
An external filter network connected to the XFC pin is not required when an external
system clock signal is applied and the PLL is disabled (MODCLK = 0 at reset). The
XFC pin must be left floating in this case.
V
SS
NORMAL OPERATING ENVIRONMENT
C3
C4
0.01 F
0.1 F
The standard filter used in normal operating environments is a single
0.1 f capacitor, connected from the XFC pin to the V
pin. An alternate filter can be used in high-stability operating environ-
ments to reduce PLL jitter under noisy system conditions. Current
systems that are operating correctly may not require this filter. If the
PLL is not enabled (MODCLK = 0 at reset), the XFC filter is not re-
quired. Versions of the SCIM that are configured for either slow or
fast reference use the same filter component values.
Figure 5-5 System Clock Filter Networks
C1
0.1 F
XFC
V
DDSYN
1
NOTE
V
SS
HIGH-STABILITY OPERATING ENVIRONMENT
C3
C4
0.01 F
0.1 F
VCO
) is either two or four times
DDSYN
C1
0.1 F
C2
0.01 F
NORMAL/HIGH-STABILITY XFC CONN
R1
18 k
supply
MOTOROLA
XFC
V
DDSYN
1, 2
5-7